This invention relates to the demodulation of differentially encoded quadriphase transmissions and more specifically, to improved demodulation thereof.
In a communication system using quadriphase transmissions, information desired to be transmitted is impressed upon a carrier signal of a given frequency by effecting predetermined phase shifts in a carrier signal corresponding to the information to be transmitted. The transmission of this carrier signal is characterized as the differentially encoded quadriphase transmission which transmits four possible information words with each word consisting of two binary bits referred to hereinafter in this application as "dibits". Differentially encoded quadriphase transmission transmits each word as a given increment in phase relative to the absolute phase of the preceding transmitted word.
In utilizing demodulators for the above-cited differentially encoded quadriphase transmissions, the demodulator determines the phase increments of the received signal and decodes the binary data from these phase increments. These phase increments are detected utilizing a reference signal. The received signal and a 90 degrees phase shifted receive signal are then multiplexed with the reference signal and a signal representing the reference signal shifted by 90 degrees. The resulting signals are fed into a plurality of integrators having an integration period equal to the period of one reference signal to obtain the detected I (in-phase) and Q (quadrature) signals from which the phase difference can be determined and proper coherent demodulation can then occur. Due to the quality of the transmission line or the like, the quality of the transmission signals deteriorate to the point that the recovery of the data transmitted is very low.
In demodulating synchronous, differentially coherent, four phase data transmission, the modulation interval or period during which the phase of the carrier frequency is altered must be determined. This period is used in establishing the modulation rate of the incoming data transmission. In addition, a dibit clock located in the receiver is synchronized with this modulation rate to establish a time frame for use in the demodulation operation. The demodulating process involves establishing a pseudo-carrier which is phase locked to the incoming carrier. This pseudo-carrier is phase locked by detecting the average phase position of the carrier over successive modulation intervals. The pseudo-carrier not only tracks the frequency of the carrier but assumes a stable phase position which can be used to establish the most probable location of the four possible carrier phases of each modulation interval. Once the phase position reference is established, the incoming carrier is investigated at each modulation interval to determine which of the four phase positions it most closely approximates. The approximated phase position is then assigned and stored as a reference for the next interval. The assigned phase position indicates the phase change and the proper two bit binary number or dibit which is then outputted as data to a receiving terminal. It is apparent that if an error is made in the assigned phase position, a false reference is established for the next interval. In generating the modulation rate, a reference oscillator is compared in a phase lock loop whose input is the modulation rate of the incoming signal and which adjust the phase of the reference oscillator to the phase of the modulation rate. As disclosed in the co-pending U.S. Application Ser. No. 129,797, filed Mar. 12, 1980, in the names of Jansen et al. now U.S. Pat. No. 4,301,417 and assigned to the assignee of the present application, it was found that in transmitting data consisting of long series of the dibits 00 and 10, the demodulator failed to decode the data due to the delay and amplitude distortion found in telephone lines. In order to overcome this problem, the application disclosed circuitry which suppressed the operation of the phase lock loop during the occurrence of the dibits 00 and 10, thereby eliminating or drastically reducing the decoding failure rate. Where long strings of the dibits 00 and 10 were transmitted, it was found that the circuit disclosed in the above-cited U.S. Application failed to provide the required synchronization necessary for a valid decoding operation. It is therefore an object of the present invention to provide a novel and improved data demodulator apparatus. It is a further object of this invention to provide a data demodulator apparatus which includes a timing and synchronization circuit which corrects for any deterioration of the quality of the transmission signal in which a long string of a predetermined dibit is involved.